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<div class="header">
  <div class="headertitle"><div class="title">TTCAN_TypeDef Struct Reference<div class="ingroups"><a class="el" href="group___c_m_s_i_s___device.html">CMSIS_Device</a> &raquo; <a class="el" href="group__stm32h723xx.html">Stm32h723xx</a> &raquo; <a class="el" href="group___peripheral__registers__structures.html">Peripheral_registers_structures</a></div></div></div>
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<p>TTFD Controller Area Network.  
 <a href="#details">More...</a></p>

<p><code>#include &lt;<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a>&gt;</code></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-pub-attribs" class="groupheader"><a id="pub-attribs" name="pub-attribs"></a>
Public Attributes</h2></td></tr>
<tr class="memitem:aff11e9728333868ba4eee8d96bd7b1d1" id="r_aff11e9728333868ba4eee8d96bd7b1d1"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aff11e9728333868ba4eee8d96bd7b1d1">TTTMC</a></td></tr>
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<tr class="memitem:a481228de486ce6fe4960b9709d0c90c9" id="r_a481228de486ce6fe4960b9709d0c90c9"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a481228de486ce6fe4960b9709d0c90c9">TTOCF</a></td></tr>
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</table>
<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<div class="textblock"><p>TTFD Controller Area Network. </p>
</div><a name="doc-variable-members" id="doc-variable-members"></a><h2 id="header-doc-variable-members" class="groupheader">Member Data Documentation</h2>
<a id="a07ab626ea35ee4ee72cd659a1c21e691" name="a07ab626ea35ee4ee72cd659a1c21e691"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a07ab626ea35ee4ee72cd659a1c21e691">&#9670;&#160;</a></span>RESERVED1</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t TTCAN_TypeDef::RESERVED1[111]</td>
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<p>Reserved, 0x144 - 0x2FC </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ab3c55cd5311babe17ea11fc1b8e35141">&#9670;&#160;</a></span>TTCPT</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t TTCAN_TypeDef::TTCPT</td>
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<p>TT Capture Time register, Address offset: 0x13C </p>

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<a id="a3bfd0b7f1b6f93b8cbc15c0239a7067d" name="a3bfd0b7f1b6f93b8cbc15c0239a7067d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a3bfd0b7f1b6f93b8cbc15c0239a7067d">&#9670;&#160;</a></span>TTCSM</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t TTCAN_TypeDef::TTCSM</td>
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<p>TT Cycle Sync Mark register, Address offset: 0x140 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a41ef32b487274b09b58f2f1aa0ac2fb8">&#9670;&#160;</a></span>TTCTC</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t TTCAN_TypeDef::TTCTC</td>
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<p>TT Cycle Time and Count register, Address offset: 0x138 </p>

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<a id="ad1333598000565e67ce606ab4df12349" name="ad1333598000565e67ce606ab4df12349"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ad1333598000565e67ce606ab4df12349">&#9670;&#160;</a></span>TTGTP</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t TTCAN_TypeDef::TTGTP</td>
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<p>TT Global Time Preset register, Address offset: 0x118 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ab6582914afd44d63dcbe34c86d597f87">&#9670;&#160;</a></span>TTIE</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t TTCAN_TypeDef::TTIE</td>
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<p>TT Interrupt Enable register, Address offset: 0x124 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ad6b6f7efcb8270de90d47c72f5f78790">&#9670;&#160;</a></span>TTILS</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t TTCAN_TypeDef::TTILS</td>
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<p>TT Interrupt Line Select register, Address offset: 0x128 </p>

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<a id="a6b78154546d3ed2f8bf410e82f19728e" name="a6b78154546d3ed2f8bf410e82f19728e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a6b78154546d3ed2f8bf410e82f19728e">&#9670;&#160;</a></span>TTIR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t TTCAN_TypeDef::TTIR</td>
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<p>TT Interrupt register, Address offset: 0x120 </p>

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<a id="a2b01e8f858a53097cb01738566b6221f" name="a2b01e8f858a53097cb01738566b6221f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a2b01e8f858a53097cb01738566b6221f">&#9670;&#160;</a></span>TTLGT</h2>

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<p>TT Local and Global Time register, Address offset: 0x134 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a0dc5f9c6576e671ec4ed4cbb214db8f8">&#9670;&#160;</a></span>TTMLM</h2>

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<p>TT Matrix Limits register, Address offset: 0x10C </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a481228de486ce6fe4960b9709d0c90c9">&#9670;&#160;</a></span>TTOCF</h2>

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<p>TT Operation Configuration register, Address offset: 0x108 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#adebe813b35b0252f726c512dec2205e1">&#9670;&#160;</a></span>TTOCN</h2>

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<p>TT Operation Control register, Address offset: 0x114 </p>

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<p>TT Operation Status register, Address offset: 0x12C </p>

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<p>TT Reference Message Configuration register, Address offset: 0x104 </p>

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<p>TT Trigger Memory Configuration register, Address offset: 0x100 </p>

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<p>TT Time Mark register, Address offset: 0x11C </p>

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<p>TT Trigger Select register, Address offset: 0x300 </p>

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<p>TUR Configuration register, Address offset: 0x110 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a6f375f5f86f7ba5bd97b0065f5e6faa0">&#9670;&#160;</a></span>TURNA</h2>

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<p>TT TUR Numerator Actual register, Address offset: 0x130 </p>

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<hr/>The documentation for this struct was generated from the following file:<ul>
<li>C:/Users/ASUS/Desktop/dm-ctrlH7-balance-9025test/Drivers/CMSIS/Device/ST/STM32H7xx/Include/<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a></li>
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